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www. belling .com.cn 1 16 - channel constant - current led driver BL8589 description the BL8589 is designed for led display applications. the device has an input shift register with corresponding data latches and 16 constant current sink drivers. the device support digital input with internal shift registers and latches, hence can be controlled directly by microprocessor - based systems. with a standard 3.3 v or 5 v logic supply, serial data input rates can reach up to 30 mhz. the BL8589 allows user defined maximum led drive current level which is set by a single external resi stor. chip build - in serial data output permits cascading of multiple devices in applications requiring additional drive lines. the BL8589 is available in a variety of 24 - terminal packages: qfn 4 4 - 24 , which ha s an exposed thermal pad, ssop - 24 and tssop - 24 . all packages are lead (pb) free and rohs compliable. features ? 16 constant - current output channels, with maximum current capability up to 50 ma each ? 3.0 to 5.5 v logic supply range ? schmitt trigger inputs for improved noise immunity ? power - on reset , all reg ister bits=0 ? low - power cmos logic and latches ? high data input rate: 30mhz ? output current accuracy: between channels < 3% and between ics 6 %, over the full operating temperature range ? internal uvlo and thermal shutdown (tsd) circuitry applications ? single - color , multicolor, or full - color led display ? single - color , multicolor, or full - color led signboard ? display backlighting ? multicolor led lighting typical application bl 8589 bl 8589 l c 9 3 0 0 v d d l c 9 3 0 0 r e x t g n d v d d v d d c o n t r o l l e r s d i s d o c l k l e o e v l e d 1 0 0 n f 1 0 0 n f 1 0 u f 1 0 u f o u t 0 o u t 1 5 o u t 0 o u t 1 5 r e x t g n d v d d s d i s d o c l k l e o e
www. belling .com.cn 2 BL8589 f unctional block diagram pin description name number description qfn44 - 24 tssop - 24 & ssop - 24 clk 6 3 3 clock, data shift clock input terminal gnd 4 1 1 ground le 7 4 4 latch enable input terminal, active high 24 21 21 o utput enable input termina l, active low out0 8 5 5 constant current outputs out1 9 6 6 out2 10 7 7 out3 11 8 8 out4 12 9 9 out5 13 10 10 out6 14 11 11 out7 15 12 12 out8 16 13 13 out9 17 14 14 out10 18 15 15 out11 19 16 16 out12 20 17 17 out13 21 18 18 out14 22 19 19 out15 23 20 20 pad - - - exposed pad for enhanced thermal dissipation, not connected internally, connect to gnd. rext 2 23 23 reference current terminal, sets output current for all channels sdi 5 2 2 serial data in terminal sdo 1 22 22 serial data out terminal vdd 3 24 24 logic supply terminal r e x t c u r r e n t r e g u l a t o r o u t p u t c o n t r o l d r i v e r s o u t 0 o u t 1 o u t 1 4 o u t 1 5 o e v d d l a t c h e s l e 1 6 b i t s s h i f t r e g i s t o r s s d i c l k s d o 1 6 b i t s 1 6 b i t s t s d u v l o v d d g n d oe
www. belling .com.cn 3 BL8589 pin configuration marking: llll: lot no. ordering information product no ordering numbe r pin package devices per reel temperature range & rohs BL8589 BL8589 cjltr qfn44 - 24 3000 - 40~150 ? c & pb free BL8589 BL8589 cpotr ssop - 24 2 000 - 40~150 ? c & pb free BL8589 BL8589 cqotr tssop - 24 2000 - 40~150 ? c & pb free absolute maximum ratings characterist ic symbol rating units supply voltage vdd 0~ 8 .0 v input voltage range v sdi , v clk , v le , v - 0. 3 ~vdd +0. 3 v out(x) output current i out(x) + 65 ma out(x) voltage range v out(x) - 0. 3 ~1 2 v clock frequency f clk 30 mhz esd rating hbm 2.0 k v cdm 1.0 k v junction temperature t j 150 ? c storage temperature t stg - 55~1 65 ? c electrical characteristics ( test conditions: t a 1 =25 ? c , vdd=3.0 to 5.5v, unless otherwise specified .) symbol parameter conditions min . typ 2 max . units v dd input voltage operating 3.0 5.0 5.5 v vdd(uv) under voltage lockout vdd 0 o ut(x) output current vdd =4.5 to 5.5v, v out (x) =1v, r rext =374 out(x) =1v, r rext =374 out(x) =1v, r rext =910 out (x) =1v, r rext =910 BL8589 BL8589 BL8589 g n d o u t 1 1 o u t 1 5 o u t 1 2 o u t 1 o u t 8 o u t 1 0 l e o u t 0 c l k o u t 5 o e o u t 2 o u t 7 2 4 t h e r m a l p a d 1 3 2 3 2 0 1 9 1 8 1 6 1 5 v d d s d i o u t 3 o u t 4 o u t 6 1 4 o u t 9 1 7 o u t 1 3 2 1 o u t 1 4 2 2 q f n 4 4 t o p v i e w s d o r e x t 1 4 5 2 3 6 8 7 1 0 9 1 1 1 2 l c 9 3 0 0 l l l l 1 g n d 2 s d i 3 c l k 4 l e 5 o u t 0 6 o u t 1 7 o u t 2 8 o u t 3 9 o u t 4 1 0 o u t 5 1 1 o u t 6 1 2 o u t 7 2 4 v d d 2 3 r e x t 2 2 s d o 2 1 o e 2 0 o u t 1 5 1 9 o u t 1 4 1 8 o u t 1 3 1 7 o u t 1 2 1 6 o u t 1 1 1 5 o u t 1 0 1 4 o u t 9 1 3 o u t 8 s s o p - 2 4 l c 9 3 0 0 l l l l t s s o p - 2 4 1 g n d 2 s d i 3 c l k 4 l e 5 o u t 0 6 o u t 1 7 o u t 2 8 o u t 3 9 o u t 4 1 0 o u t 5 1 1 o u t 6 1 2 o u t 7 2 4 v d d 2 3 r e x t 2 2 s d o 2 1 2 0 o u t 1 5 1 9 o u t 1 4 1 8 o u t 1 3 1 7 o u t 1 2 1 6 o u t 1 1 1 5 o u t 1 0 1 4 o u t 9 1 3 o u t 8 o e l c 9 3 0 0 l l l l oe
www. belling .com.cn 4 BL8589 electrical characteristics (continued) (test conditions: t a 1 =25 ? c, vdd=3.0 to 5.5v, unless otherwise specified.) i out(x) output current shift vdd =5.5v, v out(x) =1v , r rext =910 , ta=25 ? c; betw een one output on and all outputs on - - 1 % err o ut to out matching 3 v out (x) =1v, r rext =374 , all outputs on - 1 3 % v out (x) =1v, r rext =910 , all outputs on - 1 3 % i o ut(x)(reg ) output current regulation vdd=5.5v, v out (x) =1 to 3v, r rext =374 , all outputs on - 1.7 3 % vdd=5.5v, v out (x) =1 to 3v, r r ext =910 , all outputs on - 2.4 4 % vdd=3.6v, v out (x) =1 to 3v, r rext =374 , all outputs on - 1.2 2 % vdd=3.6v, v out (x) =1 to 3v, r rext =910 , all outputs on - 1.8 3 % i out(x) lk o utput leakag e current v out (x) =12v , v =logic 1 - - 0.5 u a v ih logic input vol tage 0.8*vdd - vdd v v il gnd - 0.2*gnd v v ihys logic input voltage hysteresis a ll digital inputs 250 - 900 mv i l logic input current a ll digital inputs - 1 - 1 u a v ol sdo voltage i ol =1ma - - 0.5 v v oh i oh = - 1ma vdd - 0.5 - - v i v dd(off) supply current 4 r rext =3.8k , v = logic 1 - - 6 m a r rext =910 , v = logic 1 - - 16 m a r rext =374 , v = logic 1 - - 40 m a i v dd(on) all outputs on, r rext =910 , v out(x) =1v , d ata transfer 30mhz - - 20 m a all outputs on, r rext =374 , v out (x) =1v , d ata transfer 30mhz - - 45 m a v r ext reference voltage r rext =374 - 1.21 - v t jtsd thermal shutdown temperature i ncreasing - 150 - ? c t jtsdhys thermal shutdown hysterisis temperature decreasing - 30 - ? c oe
www. belling .com.cn 5 BL8589 switc hing characteristics (test conditions: t a 1 =25 ? c, v ih = vdd= 5.0v, v out(x) =1v, v il =0v, r rext =910 , v l =2v, rl=51 , c l =15pf(see also timing section). symbol parameter conditions min typ 2 max units f clk clock frequency - - 30 mhz f clkc clock frequency (cascad e devices) - - 25 mhz t wh0 c lock pulse duration clk= logic 1 16 - - ns t wh1 le pulse duration le= logic 1 20 - - ns t su0 setup time sdi to clk 10 - - ns t su1 clk to le 10 - - ns t h0 hold time clk to sdi 10 - - ns t h1 le to clk 10 - - n s t r0 rise time sdo, 10/90% points (measurement circuit a) - - 16 ns t r1 outx, vdd =5v, 10/90% points (measurement circuit b) - 10 30 ns t f 0 fall time sdo, 10/90% points (measurement circuit a) - - 16 ns t f1 outx , vdd =5v, 10/90% points (measurement circuit b) - 10 30 ns t pd0 propagation delay time clk to sdo (measurement circuit a) - - 30 ns t pd1 to outx (measurement circuit b) - - 60 ns t pd2 le to outx (measurement circuit b) - - 60 ns t w ( ) output enable pulse duration (see timing diagrams secti on) 60 - - ns 1 tested at 25c. specifications are assured by design and characterization over the operating temperature range of C 40c to 85c. 2 typical data are for initial design estimations only, and assume optimum manufacturing and application condi tions. performance may vary for individual units, within the specified maximum and minimum limits. 3 err = (i o (min or max) C i o (av)) / i o (av). i o (av) is the average current of all outputs. i o (min or max) is the output current with the greatest difference f rom i o (av). 4 recommended operating range: v o = 1.0 to 3.0 v. input - output truth table sdi clk shift register contents sdo le latch contents output contents i 0 i 1 i 2 i 1 5 i 0 i 1 i 2 i 15 i 0 i 1 i 2 i 1 5 h h r 0 r 1 r 1 4 r 1 5 l l r 0 r 1 r 1 4 r 1 5 x r 0 r 1 r 2 r 1 5 x x x x x l r 0 r 1 r 2 r 1 5 p 0 p 1 p 2 p 1 5 h p 0 p 1 p 2 p 1 5 l p 0 p 1 p 2 p 1 5 x x x x h h iz h iz h iz h iz l = low logic (voltage) inpu t , h = high logic (voltage) input , x = dont care, p = present state, r = previous state hiz=high impedance oe oe oe
www. belling .com.cn 6 BL8589 timing diagrams o u t 3 o u t 4 o u t 5 c l k l e s d i s d o 1 4 d o n o t c a r e o n s t a t u s h i g h i m p e d a n c e o u t 0 o u t 1 o u t 2 d 1 5 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 1 5 d 1 4 o u t 1 1 o u t 1 2 o u t 1 3 o u t 8 o u t 9 o u t 1 0 d 1 d 0 o u t 6 o u t 7 o u t 1 4 o u t 1 5 d 0 d 0 d 1 d 1 5 d 1 4 1 6 oe
www. belling .com.cn 7 BL8589 timing diagrams (continued) disabling outputs o u t ( x ) t w ( o e ) 5 0 % 5 0 % 5 0 % 5 0 % t p d 1 t p d 1 9 0 % 1 0 % t r 1 t f 1 ( c u r r e n t ) oe
www. belling .com.cn 8 BL8589 p arameter mea surement circuits (a) circuit for t f0 , t pd0 , t r0 (b) circuit for t f1 , t pd1 , t pd2 and t r1 o perating characteristics application information normal operation a clk (clock) input pulse or more specifically t he rising edge of the clk starts the transfer of serial data from the sdi (seria l data in) input to the shift register. for proper and accurate transfer, the serial data must appear at the input prior to the rising edge of the clk waveform. the register stores the sdi data and forward to the sdo (serial data out) output upon succeedin g clk pulses . access to the data stored in the register from corresponding latches can be enabled by holding le high (serial - to - parallel conversion). holding (output enable) high disables the output sink drivers. while w ith active (low), the outputs are controlled by the state of their respective latches. when both le and pins are high during serial data entry the latches are bypassed. setting maximum channel c urrent the maximum individual channel output current is determined by the external resistor, r rex t , which is placed between the r ext pin and gnd. the voltage on r rex t , v re xt , is set by build - in bandgap reference, of which the typical value is 1.21v. following equations can be used to calculate the maximum channel output current: i out(x) (max) = (1 .24 / r re xt ) *15 where r re xt is the value of the external resistor, which should larger than 374 . the maximum per channel (out0 to out15) constant outpu t current i out(x) (max) as a function of values of channel output current vs out(x) voltage 15 25 35 45 0 1 2 3 v out(x) ( v ) rext=470 rext=910 channel output current vs external resistance 0 10 20 30 40 50 0 2 4 vdd=3v vdd=5v iout(x) (ma) (ma) iout(x) (ma ) rext (k ) BL8589 BL8589 1 5 p f s d o l c 9 3 0 0 c l l c 9 3 0 0 r l v l o u t ( x ) oe oe
www. belling .com.cn 9 BL8589 r re xt is shown in the operating characteristics section. under voltage lockout the BL8589 has an internal under voltage lockout (uvlo) function to ensure proper device operation. the outputs are disabled once the supply voltage drops below a minimum acceptable level. this feature is of significant importance for some critical applications. upon recovery of the supply voltage after a uvlo event, all internal shift registers and latches are set to 0. the BL8589 is then operated in normal mode. thermal shutdown protection the typical value of thermal shutdown threshold temperature t jtsd is 1 50 c. if the junction temperature exceeds this value, the outputs will be turned off. there exists a thermal shutdown hysteresis, which is typically 30 c. hence outputs are resumed once the device is cooled down and junction temperature falls below 1 35 c. however, the shift register and output latches register remain active during a thermal shutdown event. therefore, sto red data is preserved and there is no need to reset. load supply voltage (v led ) the optimum driver voltage drops (v out(x) ) for the device is in the range of 1.0 to 3.0v. higher v out(x) will result in increased package power dissipation. to minimize packag e power dissipation, it is recommended that either lowest possible load supply voltage (v led ) is used or to set a series voltage drop, v drop , according to the following equation: v drop = v led C v f C v out(x) , in which v f is the led forward voltage. v drop = i o r drop for a single driver, for a zener diode (v z ), or for a series string of silicon diodes (approximately 0.7 v per diode) for a group of drivers (these configurations are shown in the figure). if the available voltage source will cause unacceptabl e power dissipation and series resistors or diodes are undesirable, a voltage regulator can be used to provide v led . typical application voltage drops v l e d v d r o p v d s v l e d v d r o p v f v d s v f v l e d v d s v f v d r o p
www. belling .com.cn 10 BL8589 package line package qfn44 - 24 devices per reel 3 000 pcs unit mm symbol dimension (mm) symbol dimension (mm) min nom max min nom max a 0.77 0.82 0.87 ne 2 . 50 bsc a1 - 0. 01 0. 05 nd 2 . 50 bsc b 0.18 0.25 0. 32 e 3.90 4.00 4.10 4.00 4.10 c 0.18 0.20 0.22 e2 2.50ref d 3.90 4.00 4.10 l 0.35 0.40 0.45 d 2 2.50ref h 0.30 0.35 0.40 e 0.50bsc
www. belling .com.cn 11 BL8589 package line (continued) package tssop - 24 devices per reel 2 000 pcs unit mm symbol dimension (mm) symbol dimension (mm) min nom max min nom max a - - 1.77 d 8.45 8.65 8.85 a1 0. 08 0.1 8 0.2 8 e 5.8 6 .0 6.2 a2 1.2 0 1.4 0 1.6 0 e1 3.7 3.9 4.1 a3 0.55 0.65 0.75 e 0.635 bsc b 0. 23 - 0. 33 l 0.5 0.65 0.8 b1 0. 22 0. 25 0. 28 l1 1.05bsc c 0. 21 - 0.2 6 ? ? 0 - 8 c1 0.19 0.20 0.21 ?
www. belling .com.cn 12 BL8589 package line (continued) package ssop - 24 devices per re el 2 000 pcs unit mm symbol dimension (mm) symbol dimension (mm) min nom max min nom max a - - 1. 90 d 12.80 13.00 13.20 a1 0. 0 5 0. 15 e 7.70 7.90 8.10 a2 1. 40 1. 5 0 1.6 0 e1 5.80 6.00 6.20 a3 0. 47 0.6 7 0. 87 e 1.00 bsc b 0. 39 - 0. 47 l 0. 2 5 0. 4 5 0. 65 b1 0. 38 0. 40 0. 43 l1 0.9 5bsc c 0. 15 - 0.2 0 ? ? 0 - 8 c1 0.1 4 0. 15 0. 16 ?

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